Design and manufacture of a radio-frequency (RF) direct conversion receiver in a complementary metal-oxide semiconductor (CMOS) material raises challenges, including suppression of flicker noise of active components while providing sufficient sensitivity. The challenges are more complicated when an ultra-high speed digital technological process is used for a receiver implementation.
Flicker noise may arise in a baseband channel in several ways.
Flicker noise may be frequency up-converted, or mixed-up, by a strong blocker in a low-noise amplifier (LNA) due to second order non-linearity of the LNA. Up-converted flicker noise may pollute a noise floor of the LNA around the blocker frequency.
Flicker noise may arise in a conventional mixer circuit when mixer transistors generate noise directly at baseband.
LNA transistors may generate flicker noise, which may directly feed through to mixer outputs. LNA-originated flicker noise may be more pronounced when the LNA has relatively high gain at baseband.
While flicker noise may be reduced with on-die or on-chip inductors to provide resonant loads, on-die inductors are relatively bulky, radiate magnetic and electrostatic noise, and may necessitate relatively high bias currents due to relatively low impedance of corresponding resonant loads. For relatively low resistivity substrates, such as those used in ultra-high speed digital processes, it may also be difficult to accommodate relatively high-Q inductors on-die.
In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.